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HB52E48EM-B6 32 mb unbuffered sdram dimm 4-mword 64-bit, 100 mhz memory bus, 1-bank module (4 pcs of 4 m 16 components) pc100 sdram ade-203-892a (z) rev. 1.0 july 23, 1998 description the hb52e48em belongs to 8-byte dimm (dual in-line memory module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. the hb52e48em is a 4 m 64 1-bank synchronous dynamic ram module, mounted 4 pieces of 64-mbit sdram (hm5264165tt) sealed in tsop package and 1 piece of serial eeprom (2-kbit eeprom) for presence detect (pd). an outline of the products is 168-pin socket type package (dual lead out). therefore, it makes high density mounting possible without surface mount technology. it provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the module board. features fully compatible with : jedec standard outline unbuffered 8-byte dimm : intel pcb reference design (rev.1.0) 168-pin socket type package (dual lead out) ? outline: 133.37 mm (length) 34.925 mm (height) 4.00 mm (thickness) ? lead pitch: 1.27 mm 3.3 v power supply clock frequency: 100 mhz (max) lvttl interface data bus width : 64 non parity single pulsed ras 4 banks can operates simultaneously and independently burst read/write operation and burst read/single write operation capability programmable burst length: 1/2/4/8/full page
HB52E48EM-B6 2 2 variations of burst sequence ? sequential ? interleave programmable ce latency: 3 byte control by dqmb refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh ? auto refresh ? self refresh full page burst length capability ? sequential burst ? burst stop capability ordering information type no. frequency package contact pad HB52E48EM-B6 100 mhz 168-pin dual lead out socket type gold pin arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin
HB52E48EM-B6 3 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 s2 87 dq33 129 nc 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v cc 48 nc 90 v cc 132 nc 7 dq4 49 v cc 91 dq36 133 v cc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 nc 94 dq39 136 nc 11 dq8 53 nc 95 dq40 137 nc 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v cc 101 dq45 143 v cc 18 v cc 60 dq20 102 v cc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 nc 63 nc 105 nc 147 nc 22 nc 64 v ss 106 nc 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v cc 68 v ss 110 v cc 152 v ss 27 w 69 dq24 111 ce 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0 72 dq27 114 nc 156 dq59 31 nc 73 v cc 115 re 157 v cc 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63
HB52E48EM-B6 4 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 (ap) 80 nc 122 a13 (ba0) 164 nc 39 a12 (ba1) 81 wp 123 a11 165 sa0 40 v cc 82 sda 124 v cc 166 sa1 41 v cc 83 scl 125 ck1 167 sa2 42 ck0 84 v cc 126 nc 168 v cc pin description pin name function a0 to a11 address input row address a0 to a11 column address a0 to a7 a13/a12 bank select address ba0/ba1 dq0 to dq63 data input/output s0 , s2 chip select input re row enable (ras) input ce column enable (cas) input w write enable input dqmb0 to dqmb7 byte data mask ck0, ck2 clock input cke0 clock enable input wp write protect for serial pd sda data input/output for serial pd scl clock input for serial pd sa0 to sa2 serial address input v cc primary positive power supply v ss ground nc no connection
HB52E48EM-B6 5 serial pd matrix* 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes used by module manufacturer 1000000080 128 1 total spd memory size 0 0 0 0 1 0 0 0 08 256 byte 2 memory type 0 0 0 0 0 1 0 0 04 sdram 3 number of row addresses bits 0 0 0 0 1 1 0 0 0c 12 4 number of column addresses bits 0000100008 8 5 number of banks 0 0 0 0 0 0 0 1 01 1 6 module data width 0 1 0 0 0 0 0 0 40 64 7 modul e da t a wi dth (c ont i nued) 0 0 0 0 0 0 0 0 00 0 (+) 8 modul e in t er f ac e si gnal lev el s 0 0 0 0 0 0 0 1 01 lvttl 9 sdram cycle time (highest ce latency) 15 ns 10100000a0 cl = 3 10 sdram access from clock (highest ce latency) 9 ns 0110000060 11 module configuration type 0 0 0 0 0 0 0 0 00 non parity 12 refresh rate/type 1 0 0 0 0 0 0 0 80 normal (15.625 m s) self refresh 13 sdram width 0 0 0 1 0 0 0 0 10 4m 16 14 error checking sdram width 0 0 0 0 0 0 0 0 00 15 sdram device attributes: minimum clock delay for back-to-back random column addresses 0000000101 1 clk 16 sdram device attributes: burst lengths supported 1 0 0 0 1 1 1 1 8f 1, 2, 4, 8, full page 17 sdram device attributes: number of banks on sdram device 0000010004 4 18 sdram device attributes: ce latency 0000010004 3 19 sdram device attributes: cs latency 0000000101 0 20 sdram device attributes: w latency 0000000101 0 21 sdram module attributes 0 0 0 0 0 0 0 0 00 non buffer
HB52E48EM-B6 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 22 sdram device attributes: general 000011100e v cc 10% 23 sdram cycle time (2nd highest ce latency) 15 ns 0000000000 24 sdram access from clock (2nd highest ce latency) 9 ns 0000000000 25 sdram cycle time (3rd highest ce latency) undefined 0000000000 26 sdram access from clock (3rd highest ce latency) undefined 0000000000 27 minimum row precharge time 0001010014 20 ns 28 row active to row active min 0001010014 20 ns 29 re to ce delay min 0001010014 20 ns 30 minimum re pulse width 0011001032 50 ns 31 density of each bank on module 0000100008 32 m byte 32 address and command signal input setup time 0010000020 2 ns 33 address and command signal input hold time 0001000010 1 ns 34 data signal input setup time 0010000020 2 ns 35 data signal input hold time 0001000010 1 ns 36 to 61 superset information 0000000000 future use 62 spd data revision code 0001001012 rev.1.2a 63 checksum for bytes 0 to 62 0000001002 2 64 manuf ac t ur er s jedec id c ode 0000011107 hitachi 65 to 71 manuf ac t ur er s jedec id c ode 0000000000 72 manufacturing location * 3 (ascii- 8bit code) 73 manufacturers part number 0100100048 h 74 manufacturers part number 0100001042 b 75 manufacturers part number 0011010135 5 76 manufacturers part number 0011001032 2 77 manufacturers part number 0100010145 e 78 manufacturers part number 0011010034 4
HB52E48EM-B6 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 79 manufacturers part number 0011100038 8 80 manufacturers part number 0100010145 e 81 manufacturers part number 010011014d m 82 manufacturers part number 001011012d 83 manufacturers part number 0100001042 b 84 manufacturers part number 0011011036 6 85 manufacturers part number 0010000020 (space) 86 manufacturers part number 0010000020 (space) 87 manufacturers part number 0010000020 (space) 88 manufacturers part number 0010000020 (space) 89 manufacturers part number 0010000020 (space) 90 manufacturers part number 0010000020 (space) 91 revision code 0011000030 initial 92 revision code 0010000020 (space) 93 manufacturing date year code (bcd)* 4 94 manufacturing date week code (bcd)* 4 95 to 98 assembly serial number * 6 99 to 125 manufacturer specific data * 5 126 intel specification frequency 0110010064 100 mhz 127 intel specification ce # latency support 10101101ad cl = 3 notes: 1. all serial pd data are not protected. 0: serial data, driven low, 1: serial data, driven high these spd are based on intel specification (rev.1.2a). 2. regarding byte32 to 35, based on jedec committee ballot jc42.5-97-119. 3. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows j on ascii code.) 4. regarding byte93 and 94, based on jedec committee ballot jc42.5-97-135. bcd is binary coded decimal. 5. all bits of 99 through 125 are not defined (1 or 0). 6. bytes 95 through 98 are assembly serial number.
HB52E48EM-B6 8 block diagram dqmb0 dqm dq0 to dq7 dq8 to dq15 dqmb1 * d0 to d3: hm5264165 u0: 2-kbit eeprom c0 to c7: 0.33 f c8 to c11: 0.10 f c100, c101: 10 pf n0 to n17: network registor 10 w r100 to r103: 10 w r1: 47 k w v cc (d0 to d3, u0) v ss (d0 to d3, u0) serial pd sda wp r1 v ss a0 a1 a2 sa0 sa1 sa2 v ss v cc scl u0 sda scl notes : 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve r100 r101 ck0 ck1, ck3 clk :2 sdrams + 15 pf cap clk :2 sdrams + 15 pf cap 8 n0, n1 8 n2, n3 dqmb4 dq32 to dq39 dq40 to dq47 dqmb5 8 n8, n9 8 n10, n11 cke0 cke (d0 to d3) ck2 r102, r103 c100, c101 c8 to c11 c0 to c7 re , ce , w cs d2 d0 dqm cs s0 s2 "high" state. dqmb2 dqm dq16 to dq23 dq24 to dq31 dqmb3 8 n4, n5 8 n6, n7 dqmb6 dq48 to dq55 dq56 to dq63 dqmb7 8 n12, n13 8 n14, n15 cs d3 d1 dqm dqm dqm dqm dqm cs a0 to a13
HB52E48EM-B6 9 absolute maximum ratings parameter symbol value unit note voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( 4.6 (max)) v1 supply voltage relative to v ss v cc C0.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 4.0 w operating temperature topr 0 to +65 c storage temperature tstg C55 to +125 c note: 1. respect to v ss dc operating conditions (ta = 0 to +65 c) parameter symbol min max unit notes supply voltage v cc 3.0 3.6 v 1, 2 v ss 00v3 input high voltage v ih 2.0 v cc + 0.3 v 1, 4, 5 input low voltage v il C0.3 0.8 v 1, 6 notes: 1. all voltage referred to v ss 2. the supply voltage with all v cc pins must be on the same level. 3. the supply voltage with all v ss pins must be on the same level. 4. ck, cke, s , dqmb, dq pins: v ih (max) = v cc + 0.5 v for pulse width 5 ns at v cc . 5. others: v ih (max) = 4.6 v for pulse width 5 ns at v cc . 6. v il (min) = C1.0 v for pulse width 5 ns at v ss .
HB52E48EM-B6 10 v il /v ih clamp (component characteristic) this sdram component has v il and v ih clamp for ck, cke, s , dqmb and i/o pins. minimum v il clamp current v il (v) i (ma) C2 C32 C1.8 C25 C1.6 C19 C1.4 C13 C1.2 C8 C1 C4 C0.9 C2 C0.8 C0.6 C0.6 0 C0.4 0 C0.2 0 00 v il (v) i (ma) ?.5 ? ?.5 ? ?5 ?0 ?5 ?0 ?0 0 ?5 ? 0
HB52E48EM-B6 11 minimum v ih clamp current v ih (v) i (ma) v cc + 2 10 v cc + 1.8 8 v cc + 1.6 5.5 v cc + 1.4 3.5 v cc + 1.2 1.5 v cc + 1 0.3 v cc + 0.8 0 v cc + 0.6 0 v cc + 0.4 0 v cc + 0.2 0 v cc + 0 0 v ih (v) v cc + 0 v cc + 1 v cc + 2 v cc + 0.5 v cc + 1.5 i (ma) 8 4 6 0 2 10
HB52E48EM-B6 12 i ol /i oh characteristics (component characteristic) output low current (i ol ) i ol i ol vout (v) min (ma) max (ma) 00 0 0.4 27 71 0.65 41 108 0.85 51 134 1 58 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 i ol (ma) vout (v) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 min max
HB52E48EM-B6 13 output high current (i oh ) (ta = 0 to 65 c, v cc = 3.0 v to 3.45 v, v ss = 0 v) i oh i oh vout (v) min (ma) max (ma) 3.45 C3 3.3 C28 3 0 C75 2.6 C21 C130 2.4 C34 C154 2 C59 C197 1.8 C67 C227 1.65 C73 C248 1.5 C78 C270 1.4 C81 C285 1 C89 C345 0 C93 C503 i oh (ma) vout (v) 0 ?00 ?00 ?00 ?00 ?00 ?00 0.5 1 1.5 2 2.5 3 min max 3.5 0
HB52E48EM-B6 14 dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) HB52E48EM-B6 parameter symbol min max unit test conditions notes operating current i cc1 400 ma burst length = 1 t rc = min 1, 2, 3 standby current in power down i cc2p 12 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 8 ma cke = v il , t ck = 7 standby current in non power down i cc2n 80 ma cke, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 24 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 120 ma cke, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current i cc4 660 ma t ck = min, bl = 4 1, 2, 5 refresh current i cc5 560 ma t rc = min 3 self refresh current i cc6 4 ma v ih 3 v cc C 0.2 v v il 0.2 v 8 input leakage current i li C10 10 m a0 vin v cc output leakage current i lo C10 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 v i oh = C4 ma output low voltage v ol 0.4 v i ol = 4 ma notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current.
HB52E48EM-B6 15 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol max unit notes input capacitance (address) c i1 42 pf 1, 2, 4 input capacitance ( re , ce , w )c i2 43 pf 1, 2, 4 input capacitance (cke) c i3 40 pf 1, 2, 4 input capacitance ( s )c i4 25 pf 1, 2, 4 input capacitance (ck) c i5 50 pf 1, 2, 4 input capacitance (dqmb) c i6 17 pf 1, 2, 4 input/output capacitance (dq) c i/o1 15 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) HB52E48EM-B6 parameter hitachi symbol pc100 symbol min max unit notes system clock cycle time t ck tclk 10 ns 1 ck high pulse width t ckh tch 3 ns 1 ck low pulse width t ckl tcl 3 ns 1 access time from ck t ac tac 6 ns 1, 2 data-out hold time t oh toh 3 ns 1, 2 ck to data-out low impedance t lz 2 ns 1, 2, 3 ck to data-out high impedance t hz 6 ns 1, 4 data-in setup time t ds tsi 2 ns 1 data in hold time t dh thi 1 ns 1 address setup time t as tsi 2 ns 1 address hold time t ah thi 1 ns 1 cke setup time t ces tsi 2 ns 1, 5 cke setup time for power down exit t cesp tpde 2 ns 1 cke hold time t ceh thi 1 ns 1 command setup time t cs tsi 2 ns 1 command hold time t ch thi 1 ns 1
HB52E48EM-B6 16 HB52E48EM-B6 parameter hitachi symbol pc100 symbol min max unit notes ref/active to ref/active command period t rc trc 70 ns 1 active to precharge command period t ras tras 50 120000 ns 1 active command to column command (same bank) t rcd trcd 20 ns 1 precharge to active command period t rp trp 20 ns 1 write recovery or data-in to precharge lead time t dpl tdpl 15 ns 1 active (a) to active (b) command period t rrd trrd 20 ns 1 transition time (rise to fall) t t 15ns refresh period t ref 64ms notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.5 v. 2. access time is measured at 1.5 v. load condition is c l = 50 pf. 3. t lz (max) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces defines cke setup time to ck rising edge except power down exit command. test conditions input and output timing reference levels: 1.5 v input waveform and output load: see following figures t t 2.4 v 0.4 v 0.8 v 2.0 v input t t dq cl
HB52E48EM-B6 17 relationship between frequency and minimum latency parameter HB52E48EM-B6 frequency (mhz) 100 t ck (ns) hitachi symbol pc100 symbol 10 notes active command to column command (same bank) i rcd 21 active command to active command (same bank) i rc 7 = [i ras + i rp ] 1 active command to precharge command (same bank) i ras 51 precharge command to active command (same bank) i rp 21 write recovery or data-in to precharge command (same bank) i dpl tdpl 2 1 active command to active command (different bank) i rrd 21 self refresh exit time i srex tsrx 1 2 last data in to active command (auto precharge, same bank) i apw tdal 4 = [i dpl + i rp ] self refresh exit to command input i sec 7 = [i rc ] 3 precharge command to high impedance i hzp troh 3 last data out to active command (auto precharge) (same bank) i apr 1 last data out to precharge (early precharge) i ep C2 column command to column command i ccd tccd 1 write command to data in latency i wcd tdwd 0 dqmb to data in i did tdqm 0 dqmb to data out i dod tdqz 2 cke to ck disable i cle tcke 1 register set to active command i rsa tmrd 1 s to command disable i cdd 0 power down exit to command input i pec 1 burst stop to output valid data hold i bsr 2 burst stop to output high impedance i bsh 3 burst stop to write data ignore i bsw 0
HB52E48EM-B6 18 notes: 1. i rcd to i rrd are recommended value. 2. be valid [dsel] or [nop] at next command of self refresh exit. 3. except [dsel] and [nop] pin functions ck0 to ck3 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. s0 , s2 (input pin): when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. re , ce and w (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a11 (input pins): row address (ax0 to ax11) is determined by a0 to a11 level at the bank active command cycle ck rising edge. column address (ay0 to ay7) is determined by a0 to a7 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by a12/a13 (ba) is precharged. a12/a13 (input pin): a12/a13 are bank select signal (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if a12 is low and a13 is low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 is high and a13 is high, bank 3 is selected. cke0 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down and clock suspend modes. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z. write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written. dq0 to dq63 (input/output pins): data is input to and output from these pins. v cc (power supply pins): 3.3 v is applied. v ss (power supply pins): ground is connected.
HB52E48EM-B6 19 command operation command truth table the sdram module recognizes the following commands specified by the s , re , ce , w and address pins. cke command symbol n - 1 n s recew a12/a13 a 1 0 a0 to a11 ignore command desl h h no operation nop h lhhh burst stop in full page bst h lhhl column address and read command read h lhl hv l v read with auto-precharge read a h lhl hv hv column address and write command writ h lhl lv l v write with auto-precharge writ a h lhl lv hv row address strobe and bank active actv h ll hhv vv precharge select bank pre h ll hlv l precharge all bank pall h ll hl h refresh ref/self h v l l l h mode register set mrs h llllv vv note: h: v ih . l: v il . : v ih or v il . v: valid address input ignore command [desl]: when this command is set ( s is high), the sdram module ignore command input at the clock. however, the internal status is held. no operation [nop]: this command is not an execution command. however, the internal operations continue. burst stop in full-page [bst]: this command stops a full-page burst operation (burst length = full-page) and is illegal otherwise. when data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is determined by the column address and the bank select address (ba). after the read operation, the output buffer becomes high-z. read with auto-precharge [read a]: this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. when the burst length is full-page, this command is illegal.
HB52E48EM-B6 20 column address strobe and write command [writ]: this command starts a write operation. when the burst write mode is selected, the column address and the bank select address (ba) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address and the bank select address (ba). write with auto-precharge [writ a]: this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. when the burst length is full-page, this command is illegal. row address strobe and bank activate [actv]: this command activates the bank that is selected by bank select address (ba) and determines the row address (ax0 to ax11). when a12 and a13 are low, bank 0 is activated. when a12 is high and a13 is low, bank 1 is activated. when a12 is low and a13 is high, bank 2 is activated. when a12 and a13 are high, bank 3 is activated. precharge selected bank [pre]: this command starts precharge operation for the bank selected by a12/a13. if a12 and a13 are low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 and a13 are high, bank 3 is selected. precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts the refresh operation. there are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke truth table section. mode register set [mrs]: the sdram module has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to a13) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register.
HB52E48EM-B6 21 dqmb truth table cke command symbol n - 1 n dqmb write enable/output enable enb h l write inhibit/output disable mask h h note: h: v ih . l: v il . : v ih or v il . write: i did is needed. read: i dod is needed. the sdram module can mask input/output data by means of dqmb. during reading, the output buffer is set to low-z by setting dqmb to low, enabling data output. on the other hand, when dqmb is set to high, the output buffer becomes high-z, disabling data output. during writing, data is written by setting dqmb to low. when dqmb is set to high, the previous data is held (the new data is not written). desired data can be masked during burst read or burst write by setting dqmb. for details, refer to the dqmb control section of the sdram module operating instructions. cke truth table cke current state command n - 1 n s recew address active clock suspend mode entry h l h any clock suspend l l clock suspend clock suspend mode exit l h idle auto-refresh command (ref) h h lllh idle self-refresh entry (self) h llllh idle power down entry h l l h h h hl h self refresh self refresh exit (selfx) l h l h h h lhh power down power down exit l h l h h h lhh note: h: v ih . l: v il . : v ih or v il .
HB52E48EM-B6 22 clock suspend mode entry: the sdram module enters clock suspend mode from active mode by setting cke to low. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend: this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read with auto-precharge suspend: the data being output is held (and continues to be output). write suspend and writ with auto-precharge suspend: in this mode, external signals are not accepted. however, the internal state is held. clock suspend: during clock suspend mode, keep the cke to low. clock suspend mode exit: the sdram module exits from clock suspend mode by setting cke to high during the clock suspend state. idle: in this state, all banks are not selected, and completed precharge operation. auto-refresh command [ref]: when this command is input from the idle state, the sdram module starts auto-refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams.) during the auto-refresh operation, refresh address and bank select address are generated inside the sdram module. for every auto-refresh cycle, the internal address counter is updated. accordingly, 4096 times are required to refresh the entire memory. before executing the auto-refresh command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto- refresh, no precharge command is required after auto-refresh. self-refresh entry [self]: when this command is input during the idle state, the sdram module starts self-refresh operation. after the execution of this command, self-refresh continues while cke is low. since self-refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry: when this command is executed during the idle state, the sdram module enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self-refresh exit: when this command is executed during self-refresh mode, the sdram module can exit from self-refresh mode. after exiting from self-refresh mode, the sdram module enters the idle state. power down exit: when this command is executed at the power down mode, the sdram module can exit from power down mode. after exiting from power down mode, the sdram module enters the idle state.
HB52E48EM-B6 23 function truth table the following table shows the operations that are performed when each command is issued in each mode of the sdram module. the following table assumes that cke is high. current state srecew address command operation precharge h desl enter idle after t rp lhhh nop enter idle after t rp lhhl bst nop l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv illegal* 4 l l h l ba, a10 pre, pall nop* 6 ll lh ref, self illegal l l l l mode mrs illegal idle h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a illegal* 5 l h l l ba, ca, a10 writ/writ a illegal* 5 l l h h ba, ra actv bank and row active l l h l ba, a10 pre, pall nop ll lh ref, self refresh l l l l mode mrs mode register set row active h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a begin read l h l l ba, ca, a10 writ/writ a begin write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall precharge ll lh ref, self illegal l l l l mode mrs illegal
HB52E48EM-B6 24 current state srecew address command operation read h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop to full page l h l h ba, ca, a10 read/read a continue burst read to ce latency and new read l h l l ba, ca, a10 writ/writ a term burst read/start write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst read and precharge ll lh ref, self illegal l l l l mode mrs illegal read with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 4 ll lh ref, self illegal l l l l mode mrs illegal write h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop on full page l h l h ba, ca, a10 read/read a term burst and new read l h l l ba, ca, a10 writ/writ a term burst and new write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst write and precharge* 2 ll lh ref, self illegal l l l l mode mrs illegal
HB52E48EM-B6 25 current state srecew address command operation write with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal* 4 l h l l ba, ca, a10 writ/writ a illegal* 4 l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 4 ll lh ref, self illegal l l l l mode mrs illegal refresh (auto- refresh) h desl enter idle after t rc lhhh nop enter idle after t rc lhhl bst enter idle after t rc l h l h ba, ca, a10 read/read a illegal* 5 l h l l ba, ca, a10 writ/writ a illegal* 5 l l h h ba, ra actv illegal* 5 l l h l ba, a10 pre, pall illegal* 5 ll lh ref, self illegal l l l l mode mrs illegal notes: 1. h: v ih . l: v il . : v ih or v il . the other combinations are inhibit. 2. an interval of t dpl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, this operation is illegal. 4. illegal for same bank, except for another bank. 5. illegal for all banks. 6. nop for same bank, except for another bank.
HB52E48EM-B6 26 from precharge state, command operation to [desl], [nop] or [bst]: when these commands are executed, the sdram module enters the idle state after t rp has elapsed from the completion of precharge. from idle state, command operation to [desl], [nop], [bst], [pre] or [pall]: these commands result in no operation. to [actv]: the bank specified by the address pins and the row address is activated. to [ref], [self]: the sdram module enters refresh mode (auto-refresh or self-refresh). to [mrs]: the sdram module enters the mode register set cycle. from row active state, command operation to [desl], [nop] or [bst]: these commands result in no operation. to [read], [read a]: a read operation starts. (however, an interval of t rcd is required.) to [writ], [writ a]: a write operation starts. (however, an interval of t rcd is required.) to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands set the sdram module to precharge mode. (however, an interval of t ras is required.) from read state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: data output by the previous read command continues to be output. after ce latency, the data output resulting from the next command will start. to [writ], [writ a]: these commands stop a burst read, and start a write cycle. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop a burst read, and the sdram module enters precharge mode.
HB52E48EM-B6 27 from read with auto-precharge state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed, and the sdram module then enters precharge mode. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from write state, command operation to [desl], [nop]: these commands continue write operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: these commands stop a burst and start a read cycle. to [writ], [writ a]: these commands stop a burst and start the next write cycle. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop burst write and the sdram module then enters precharge mode. from write with auto-precharge state, command operation to [desl], [nop]: these commands continue write operations until the burst is completed, and the sdram module enters precharge mode. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from refresh state, command operation to [desl], [nop], [bst]: after an auto-refresh cycle (after t rc ), the sdram module automatically enters the idle state.
HB52E48EM-B6 28 simplified state diagram precharge write suspend read suspend row active idle idle power down auto refresh self refresh mode register set power on writea writea suspend reada reada suspend active clock suspend sr entry sr exit mrs refresh cke cke_ active write read write with ap read with ap power applied cke cke_ cke cke_ cke cke_ cke cke_ cke cke_ precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge bst (on full page) bst (on full page) *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
HB52E48EM-B6 29 mode register configuration the mode register is set by the input to the address pins (a0 to a13) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. a13, a12, a11, a10, a9 a8: (opcode): the sdram module has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. if this pin is high, the vender test mode is set. a6, a5, a4: (lmode): these pins specify the ce latency. a3: (bt): a burst type is specified. when full-page burst is performed, only "sequential" can be selected. a2, a1, a0: (bl): these pins specify the burst length. a2 a1 a0 burst length 00 0 1 00 1 2 01 0 4 01 1 8 1 1 1 f.p. bt=0 bt=1 10 0 r 11 0 r 1 2 4 8 r r r a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 00 0 r 00 1 r 01 0 r 01 1 3 1xx r a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl a9 0 0r write mode a8 0 1 burst read and burst write 1 burst read and single write 0 1r 1 10 1 r r f.p. = full page r is reserved (inhibit) x: 0 or 1 a11 a10 a10 x x x a11 x x x 00 a12 a13 a13 x x x 0 a12 x x x 0
HB52E48EM-B6 30 burst sequence a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequential 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequential starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequential starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
HB52E48EM-B6 31 operation of the sdram module read/write operations bank active: before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (actv) command. bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the bank select address (ba) pin, and the row address (ax0 to ax11) is activated by the a0 to a11 pins at the bank active command cycle. an interval of t rcd is required between the bank active command input and the following read/write command input. read operation: a read operation starts when a read command is input. output buffer becomes low-z in the ( ce latency - 1) cycle after read command set. the sdram module can perform a burst read operation. the burst length can be set to 1, 2, 4, 8 or full-page. the start address for a burst read is specified by the column address and the bank select address (ba) at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the ce latency. the ce latency can be set to 3. when the burst length is 1, 2, 4 or 8, the dout buffer automatically becomes high-z at the next clock after the successive burst-length data has been output. the ce latency and burst length must be specified at the mode register. ce latency read ck command dout actv row column address cl = 3 out 0 out 1 out 2 out 3 t rcd cl = ce latency burst length = 4
HB52E48EM-B6 32 burst length read ck command dout actv row column out 0 out 6 out 7 out 8 address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 bl = 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 6 out 7 out 4 out 5 out 0-1 out 0 out 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd bl : burst length ce latency = 3 write operation: burst write or single write mode is selected by the opcode (a13, a12, a11, a10, a9, a8) of the mode register. 1. burst write: a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. the write start address is specified by the column address and the bank select address (ba) at the write command set cycle. writ ck command din actv row column in 0 in 6 in 7 in 8 address in 1 in 4 in 5 in 3 bl = 1 in 6 in 7 in 4 in 5 in 0-1 in 0 in 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd in 0 in 0 in 0 in 0 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 ce latency = 3
HB52E48EM-B6 33 2. single write: a single write operation is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address and the bank select address (ba) specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). writ ck command din actv row column in 0 address t rcd auto precharge read with auto-precharge: in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval defined by l apr is required before execution of the next command. ce latency precharge start cycle 3 2 cycle before the final data is output burst read (burst length = 4) clk l apr cl=3 command dq (input) note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". l ras actv read a actv out3 out2 out1 out0
HB52E48EM-B6 34 write with auto-precharge: in this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval of l apw is required between the final valid data input and input of next command. burst write (burst length = 4) ck command din l apw i ras actv writ a in0 in1 in2 in3 actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". single write ck command din l apw i ras actv writ a in actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ".
HB52E48EM-B6 35 full-page burst stop burst stop command during burst read: the burst stop (bst) command is used to stop data output during a full-page burst. the bst command sets the output buffer to high-z and stops the full-page burst read. the timing from command input to the last data changes depending on the ce latency setting. in addition, the bst command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8. ce latency bst to valid data bst to high impedance 323 ce latency = 3, burst length = full page l = 2 cycle bsr ck command dout out out out out l = 3 cycle bsh bst out out out burst stop command at burst write: the burst stop command (bst command) is used to stop data input during a full-page burst write. no data is written in the same clock as the bst command, and in subsequent clocks. in addition, the bst command is only valid during full-page burst mode, and is illegal with burst lengths of 1, 2, 4 and 8. and an interval of t dpl is required between last data-in and the next precharge command. burst length = full page t ck command din in dpl in pre/pall bst i = 0 cycle bsw
HB52E48EM-B6 36 command intervals read command to read command interval: 1. same bank, same row address: when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (same row address in same bank) ck command dout out b3 address out b1 out b2 ba actv row column a read read column b out a0 out b0 bank0 active column =a read column =b read column =a dout column =b dout ce latency = 3 burst length = 4 bank 0 2. same bank, different row address: when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (different bank) ck command dout out b3 address out b1 out b2 ba actv row 0 row 1 actv read column a out a0 out b0 bank0 active bank3 active bank0 read bank3 read read column b bank0 dout bank3 dout ce latency = 3 burst length = 4
HB52E48EM-B6 37 write command to write command interval: 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. in the case of burst writes, the second write command has priority. write to write command interval (same row address in same bank) ck command din in b3 address in b1 in b2 ba actv row column a writ writ column b in a0 in b0 bank0 active column =a write column =b write burst write mode burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. in the case of burst write, the second write command has priority. write to write command interval (different bank) ck command din in b3 address in b1 in b2 ba actv row 0 row 1 actv writ column a in a0 in b0 bank0 active bank3 active bank0 write bank3 write writ column b burst write mode burst length = 4
HB52E48EM-B6 38 read command to write command interval: 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. however, dqmb must be set high so that the output buffer becomes high-z before data input. read to write command interval (1) ck command dout in b2 in b3 read writ in b0 in b1 high-z din dqmb cl = 3 burst length = 4 burst write read to write command interval (2) ck command dout read writ din dqmb cl = 3 2 clock high-z 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, dqmb must be set high so that the output buffer becomes high-z before data input.
HB52E48EM-B6 39 write command to read command interval: 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. write to read command interval (1) ck command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout ce latency dqmb burst write mode ce latency = 3 burst length = 4 bank 0 write to read command interval (2) ck command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout ce latency in a1 dqmb burst write mode ce latency = 3 burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
HB52E48EM-B6 40 read with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. the internal auto-precharge of one bank starts at the next clock of the second command. read with auto precharge to read command interval (different bank) ck command ba dout read a read out a0 out a1 out b0 out b1 ce latency = 3 burst length = 4 bank0 read a bank3 read note: internal auto-precharge starts at the timing indicated by " ". 2. same bank: the consecutive read command (the same bank) is illegal. write with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write command (another bank) is executed. in the case of burst writes, the second write command has priority. the internal auto-precharge of one bank starts at the next clock of the second command . write with auto precharge to write command interval (different bank) ck command ba din writ a writ in b1 in b2 in b3 in a0 in a1 in b0 burst length = 4 bank0 write a bank3 write note: internal auto-precharge starts at the timing indicated by " ". 2. same bank: the consecutive write command (the same bank) is illegal.
HB52E48EM-B6 41 read with auto precharge to write command interval different bank: when some banks are in the active state, the second write command (another bank) is executed. however, dqmb must be set high so that the output buffer becomes high-z before data input. the internal auto-precharge of one bank starts at the next clock of the second command. read with auto precharge to write command interval (different bank) ck command ba dout din read a writ in b0 in b1 in b2 in b3 burst length = 4 bank0 read a bank3 write note: internal auto-precharge starts at the timing indicated by " ". dqmb cl = 3 high-z 2. same bank: the consecutive write command from read with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command.
HB52E48EM-B6 42 write with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. however, in case of a burst write, data will continue to be written until one clock before the read command is executed. the internal auto-precharge of one bank starts at the next clock of the second command. write with auto precharge to read command interval (different bank) ck command ba dout din writ a read out b0 out b1 out b2 out b3 ce latency = 3 burst length = 4 bank0 write a bank3 read note: internal auto-precharge starts at the timing indicated by " ". dqmb in a0 2. same bank: the consecutive read command from write with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command.
HB52E48EM-B6 43 read command to precharge command interval (same bank): when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. however, since the output buffer then becomes high-z after the clocks defined by l hzp , there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by l ep must be assured as an interval from the final data output to precharge command execution. read to precharge command interval (same bank): to output all data ce latency = 3, burst length = 4 ck command dout read pre/pall out a0 out a1 out a2 out a3 cl=3 l = -2 cycle ep read to precharge command interval (same bank): to stop output data ce latency = 3, burst length = 1, 2, 4, 8, full pqge burst ck command dout read pre/pall out a0 high-z l hzp = 3
HB52E48EM-B6 44 write command to precharge command interval (same bank): when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. however, if the burst write operation is unfinished, the input data must be masked by means of dqmb for assurance of the clock defined by t dpl . write to precharge command interval (same bank): burst length = 4 (to stop write operation) ck command din writ pre/pall t dpl dqmb ck in a0 in a1 command din writ pre/pall dqmb t dpl burst length = 4 (to write all data) ck in a0 in a1 in a2 command din writ pre/pall in a3 dqmb t dpl
HB52E48EM-B6 45 bank active command interval: 1. same bank: the interval between the two bank-active commands must be no less than t rc . bank active to bank active for same bank ck command address ba bank 0 active actv row actv row bank 0 active t rc 2. in the case of different bank-active commands: the interval between the two bank-active commands must be no less than t rrd . bank active to bank active for different bank ck command address ba bank 0 active bank 3 active actv row:0 actv row:1 t rrd
HB52E48EM-B6 46 mode register set to bank-active command interval: the interval between setting the mode register and executing a bank-active command must be no less than l rsa . ck command address mode register set bank active mrs actv i rsa bs & row code dqmb control the dqmb mask the dq data. the timing of dqmb is different during reading and writing. reading: when data is read, the output buffer can be controlled by dqmb. by setting dqmb to low, the output buffer becomes low-z, enabling data output. by setting dqmb to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the latency of dqmb during reading is 2 clocks. writing: input data can be masked by dqmb. by setting dqmb to low, data can be written. in addition, when dqmb is set to high, the corresponding data is not written, and the previous data is held. the latency of dqmb during writing is 0 clock.
HB52E48EM-B6 47 reading ck dout out 0 out 1 l = 2 latency out 3 dod dqmb high-z writing ck din in 0 in 1 l = 0 latency in 3 did dqmb
HB52E48EM-B6 48 refresh auto-refresh: all the banks must be precharged before executing an auto-refresh command. since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the row addresses.) the output buffer becomes high-z after auto-refresh start. in addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. self-refresh: after executing a self-refresh command, the self-refresh operation continues while cke is held low. during self-refresh operation, all row addresses are refreshed by the internal refresh timer. a self-refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto- refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) enter self-refresh mode within 15.6 m s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 m s after exiting from self-refresh mode. others power-down mode: the sdram module enters power-down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram module exits from the power down mode, and command input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode: by driving cke to low during a bank-active or read/write operation, the sdram module enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the sdram module terminates clock suspend mode, and command input is enabled from the next clock. for details, refer to the "cke truth table". power-up sequence: the sdram module should be gone on the following sequence with power up. the ck, cke, s , dqmb and dq pins keep low till power stabilizes. the ck pin is stabilized within 100 m s after power stabilizes before the following initialization sequence. the cke and dqmb is driven to high between power stabilizes and the initialization sequence. this sdram module has v cc clamp diodes for ck, cke, s , dqmb and dq pins. if these pins go high before power up, the large current flows from these pins to v cc through the diodes. initialization sequence: when 200 m s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (pall). after t rp delay, set 8 or more auto refresh commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by keeping dqmb to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contention on memory system formed with a number of device.
HB52E48EM-B6 49 v cc power up sequence initialization sequence 100 s 0 v low low low cke, dqmb ck s , dq 200 s power stabilize
HB52E48EM-B6 50 timing waveforms read cycle bank 0 active bank 0 read ck cke s t ras t rcd t ch t cs re ce w ba a10 address dqmb din dout t ch t cs t ckh t t ck ckl t rp t rc ce latency = 3 burst length = 4 bank 0 access = v or v t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as v ih ih il bank 0 precharge t ac t ac t ac t oh t oh t oh t oh t ac t lz t hz
HB52E48EM-B6 51 write cycle ck cke s t ras t rcd re ce w ba a10 address din dout t ch t cs t ckh t t ck t dh t dh ckl t dh t dh t ds t ds t ds t ds t rp t rc t dpl bank 0 write t ch t cs bank 0 active bank 0 precharge t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ah t as t ah t as t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as v ih ce latency = 3 burst length = 4 bank 0 access = v or v ih il dqmb
HB52E48EM-B6 52 mode register set cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ck cke s re ce w ba address dqmb din dout high-z b b+3 b b?1 b?2 b?3 l valid c: b rsa code l rcd l rp precharge if needed mode register set bank 3 active bank 3 read r: b c: b output mask v ih l = 3 ce latency = 3 burst length = 4 = v or v ih il rcd
HB52E48EM-B6 53 read cycle/write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 cke re s ce w address dqmb dout din ck ba r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 bank 0 active bank 0 read bank 3 active bank 3 read bank 3 read bank 3 read bank 0 precharge bank 3 precharge bank 0 active bank 0 write bank 3 active bank 3 write bank 3 write bank 3 write bank 0 precharge bank 3 precharge cke re s ce w address dqmb din dout ba high-z high-z v ih v ih read cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il write cycle re - ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il
HB52E48EM-B6 54 read/single write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:a' r:a c:a c:a a a a a bank 0 active bank 0 read bank 3 active bank 0 write bank 0 precharge bank 3 precharge bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 3 active c:a bank 0 read a a+1 a+2 a+3 bank 0 write bank 0 write cke re s ce w address dqmb din dout ck ba cke re s ce w address dqmb ba c:b bc a+1 a+3 a+1 a+2 a+3 c:c v ih v ih read/single write re , ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il din dout
HB52E48EM-B6 55 read/burst write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:a' r:a c:a c:a a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 3 active cke re s ce w address dqmb ck ba cke re s ce w address dqmb ba a+1 a+2 a+3 a a+3 a bank 0 active bank 0 read bank 3 active clock suspend bank 0 write bank 0 precharge bank 3 precharge v ih read/burst write re , ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il din dout din dout
HB52E48EM-B6 56 full page read/write cycle high-z r:a c:a r:b r:a c:a r:b high-z bank 0 active bank 0 read bank 3 active burst stop bank 3 precharge bank 0 active bank 0 write bank 3 active burst stop bank 3 precharge cke re s ce w address dqmb din dout ck ba cke re s ce w address dqmb ba v ih v ih a a+1 a+2 a+3 read cycle re , ce delay = 3 ce latency = 3 burst length = full page = v or v ih il write cycle re , ce delay = 3 ce latency = 3 burst length = full page = v or v ih il a a+1 a+2 a+3 a+6 a+5 a+4 din dout
HB52E48EM-B6 57 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ck cke s ce w ba address dqmb din dout high-z rp precharge if needed auto refresh active bank 0 t rc t rc t auto refresh read bank 0 r:a c:a a10=1 re a a+1 v ih refresh cycle and read cycle re , ce delay = 2 ce latency = 3 burst length = 4 = v or v ih il self refresh cycle ck cke s re ce w ba address dqmb din dout precharge command if needed self refresh entry command auto refresh self refresh exit ignore command or no operation cke low a10=1 rc t rp t self refresh cycle re , ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il high-z next clock enable rc t next clock enable l srex self refresh entry command
HB52E48EM-B6 58 clock suspend mode 0123 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b a a+1 a+2 a+3 b b+1 b+2 r:a c:a r:b c:b a a+1 a+2 b b+1 b+2 b+3 c:b bank0 active active clock suspend start active clock supend end bank0 read bank3 active read suspend end bank0 precharge bank3 read precharge bank0 write bank0 active active clock suspend start active clock suspend end bank3 active write suspend start write suspend end bank3 write bank0 precharge earliest bank3 precharge b+3 cke re s ce w address dqmb ck ba cke re s ce w address dqmb ba a+3 high-z high-z t ces t ceh t ces read cycle re , ce delay = 2 ce latency = 3 burst length = 4 = v or v ih il write cycle re , ce delay = 2 ce latency = 3 burst length = 4 = v or v ih il dout din dout din read suspend start earliest bank3
HB52E48EM-B6 59 power down mode ck cke s re ce w ba address dqmb din dout precharge command if needed power down entry active bank 0 power down mode exit cke low r: a a10=1 rp t high-z power down cycle re , ce delay = 3 ce latency = 3 burst length = 4 = v or v ih il initialization sequence 78910 52 53 54 48 49 50 51 auto refresh bank active if needed rc t rc t auto refresh valid 0 123456 ck cke s re ce w address dqmb dq t valid rsa t rp all banks precharge mode register set v ih v ih 55 high-z code
HB52E48EM-B6 60 physical outline 6.35 0.250 6.35 0.250 1.00 0.039 detail b detail c detail a 0.20 0.15 2.50 0.20 0.010 0.0004 0.098 0.008 3.125 0.125 3.125 0.125 0.123 0.005 0.123 0.005 1.27 0.050 3.00 typ 133.37 0.15 0.118 typ 5.251 0.006 3.00 0.10 0.118 0.004 11.43 36.83 54.61 0.450 2.150 (63.67) (2.51) 1.450 a b c 1 84 front side back side 85 4.00 0.10 0.157 0.004 17.80 0.70 34.925 1.375 168 2 ? f 3.00 0.10 2 ? f 0.118 0.003 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 4.175 0.164 2.00 0.10 0.079 0.004 (datum -a-) (datum -a-) unit: mm inch (datum -a-) r full r full note: tolerance on all dimensions 0.15/0.006 unless otherwise specified. 127.35 0.15 5.014 0.006 component area (front) component area (back) 1.27 0.10 4.00 min 0.157 min 0.050 0.004 4.00 max 0.157 max
HB52E48EM-B6 61 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca 94005-1897 tel: <1> (800) 285-1601 fax: <1> (303) 297-0447 for further information write to:
HB52E48EM-B6 62 revision record rev. date contents of modification drawn by approved by 0.0 feb. 20, 1998 initial issue (referred to hm5264165/hm5264805/hm5264405-b60 rev 0.2) t. sato k. tsuneda 1.0 jul. 23, 1998 (referred to hm5264165/hm5264805/hm5264405-b60 rev 1.0) change of word: cycle to clock : a12/a13 to ba (in figures and timing) addition of fuatures pin arrangement correct error: pin no.81 nc to wp pin description correct errors: addition of wp serial pd matrix change of byte no. 63 change of based intel specification: rev.1.2 to rev.1.2a change of title recommended dc operating conditions to dc operating conditions dc operating conditions: addition of notes 2 to 3 capacitance deletion of typ value c |1 to c i/o1 max: tbd to 42/43/40/25/50/17/15 pf ac characteristics correct error: notes 5 cke rising to ck rising relationship between frequency and minimum latency change of notes 2 and addition of notes 3 addition of description for burst stop in full-page function truth table addition of description and notes 6 change of figures for command interval auto precharge, power-up sequence write to read command interval (1) and (2), change of description for self-refresh, power-up sequence and initialization sequence change of timing waveforms read/single write cycle and clock suspend mode

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